In the semiconductor production industry, various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
Ion implantation is another processing step commonly used in the fabrication of the integrated circuits on the wafer. Ion implantation is a form of doping, in which a substance is embedded into the crystal structure of the semiconductor substrate to modify the electronic properties of the substrate. Ion implantation is a physical process which involves driving high-energy ions into the substrate using a high-voltage ion bombardment. The process usually follows the photolithography step in the fabrication of the circuits on the wafer.
The ion implantation process is carried out in an ion implanter, which generates positively-charged dopant ions in a source material. A mass analyzer separates the ions from the source material to form a beam of the dopant ions, which is accelerated to a high velocity by a voltage field. The kinetic energy attained by the accelerated ions enables the ions to collide with and become embedded in the silicon crystal structure of the substrate. Finally, the doped silicon substrate is subjected to a thermal anneal step to activate the dopant ions.
A phenomenon which commonly results from the ion implantation process is wafer charging, in which positive ions from the ion beam strike the wafer and accumulate in the masking layer. This can cause an excessive charge buildup on the wafer, leading to charge imbalances in the ion beam and beam blow-up, which results in substantial variations in ion distribution across the wafer. The excessive charge buildup can also damage surface oxides, including gate oxides, leading to device reliability problems, as well as cause electrical breakdown of insulating layers within the wafer and poor device yield.
Wafer charging is controlled using a plasma flood system, in which the wafer is subjected to a stable, high-density plasma environment. Low-energy electrons are extracted from an argon or xenon plasma in an arc chamber and introduced into the ion beam, which carries the electrons to the wafer so that positive surface charges on the wafer are neutralized. The energy of the electrons is sufficiently low to prevent negative charging of the wafer.
The performance of semiconductor devices is affected by the distribution of dopant atoms in silicon in regions such as pn junctions, epilayers, and the doping of polysilicon. Typically, semiconductor fabrication processes utilize dopant concentrations which range from about 1010 atoms/cm2 to about 1018 atoms/cm2. Various techniques have been devised for determining the dopant concentration, or dose, in silicon. These include an in-line four-point probe method, which is typically used to measure high dopant concentrations. The thermal wave system is another in-line system and is used to measure low dopant concentrations. Secondary-ion mass spectrometry (SIMS) has recently been developed for off-line measurements of dopant concentration. Other tests commonly used to determine dopant concentration in silicon include the sheet resistance test and the capacitance-voltage (C-V) test.
The sheet resistance test, capacitance-voltage test and thermal wave test each utilizes indirect techniques to measure the concentration of dopant in silicon. Consequently, the analytical accuracy of these methods is significantly affected by both the presence of other ions in the crystalline silicon matrix and the various annealing conditions used in the ion implantation process. Establishing the accuracy of the dopant concentration in silicon using conventional methods is difficult, due mainly to the silicon matrix effect on the yield of ions obtained by the ion bombardment of the ion implantation process.
Currently, no method is available to accurately quantify the concentration of dopant ions implanted in silicon on a wafer. Accordingly, calibration standards are needed for accurately quantifying the concentration of dopant atoms or impurities implanted in silicon in order to control the ion implantation dopant dose and impurity concentration in the silicon.
An object of the present invention is to provide novel calibration standards for quantifying the total concentration or dose of a dopant or impurity for ion implantation in a silicon matrix.
Another object of the present invention is to provide novel calibration standards for accurately quantifying the concentration of a dopant or impurity in a silicon matrix.
Still another object of the present invention is to provide novel calibration standards which utilize standard samples of known dopant or impurity concentrations to plot a calibration curve that is used to quantify various concentrations of a dopant or impurity in silicon.
Yet another object of the present invention is to provide novel, multi-point calibration standards which are useful in accurately and precisely quantifying dopant and impurity concentrations in a silicon matrix in order to control the dose quantity and impurity concentration in the silicon.
Still another object of the present invention is to provide a method for preparing novel calibration standards, according to which method a dopant or impurity is incorporated at various dopant/silicon or impurity/silicon atomic ratios into respective silicon matrices on multiple calibration standard wafers of a set of wafers; the atomic concentrations of the dopant or impurity in the silicon matrices are determined; and a calibration curve is formulated in which the ratio of the dopant or impurity atoms to silicon atoms in each silicon matrix is plotted versus the atomic concentration of the dopant or impurity in that silicon matrix, such that the atomic concentration of the dopant or impurity in a silicon matrix on actual wafers can be determined based on the dopant/silicon or impurity/silicon ratio in the silicon matrix.